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rev: 1.00b 12/2002 1/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 512k x 18, 256k x 32, 256k x 36 9mb sync burst srams 5.5 ns?8.5 ns 2.5 v or 3.3 v v dd 2.5 v or 3.3 v i/o 100-pin tqfp commercial temp industrial temp features ? flow through mode operation; pin 14 = no connect ? 2.5 v or 3.3 v +10%/?10% core power supply ? 2.5 v or 3.3 v i/o supply ? lbo pin for linear or interleaved burst mode ? internal input resistors on mode pins allow floating mode pins ? byte write (bw ) and/or global write (gw ) operation ? internal self-timed write cycle ? automatic power-down for portable applications ? jedec-standard 100- lead tqfp package functional description applications the gs880f18/32/36bt is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous sram with a 2-bit burst address counter. although of a type originally developed for level 2 cache applications supporting high performance cpus, the device now finds application in synchronous sram applications, ranging from dsp main store to networking chip set support. controls addresses, data i/os, chip enables (e1 , e2, e3 ), address burst control inputs (adsp , adsc , adv ), and write control inputs (bx , bw , gw ) are synchronous and are controlled by a positive-edge-triggered clock input (ck). output enable (g ) and power down control (zz) ar e asynchronous inputs. burst cycles can be initiated with either adsp or adsc inputs. in burst mode, subsequent burst addresses are generated internally and are controlled by adv . the burst address counter may be configured to count in either linear or interleave order with the linear burst order (lbo ) input. the burst function need not be used. new addresses can be loaded on every cycle with no degradation of chip performance. designing for compatibility the jedec standard for bu rst rams calls for a ft mode pin option on pin 14. board sites for flow through burst rams should be designed with v ss connected to the ft pin location to ensure the broadest access to multiple vendor sources. boards designed with ft pin pads tied low may be stuffed with gsi?s pipeline/flow through-c onfigurable burst rams or any vendor?s flow through or configurable burst sram. boards designed with the ft pin location tied high or floating must employ a non-configurable flow through burst ram, like this ram, to achieve flow through functionality. byte write and global write byte write operation is performed by using byte write enable (bw ) input combined with one or more individual byte write signals (bx ). in addition, global write (gw ) is available for writing all bytes at one time, regardless of the byte write control inputs. sleep mode low power (sleep mode) is attained through the assertion (high) of the zz signal, or by stopping the clock (ck). memory data is retained during sleep mode. core and interface voltages the gs880f18/32/36bt operates on a 2.5 v or 3.3 v power supply. all input are 3.3 v and 2.5 v compatible. separate output power (v ddq ) pins are used to decouple output noise from the internal ci rcuits and are 3.3 v and 2.5 v compatible. -5.5 -6 -6.5 -7 -7.5 -8.5 unit flow through 2-1-1-1 t kq tcycle 5.5 5.5 6.0 6.0 6.5 6.5 7.0 7.0 7.5 7.5 8.5 8.5 ns ns 3.3 v curr (x18) curr (x32/x36) 175 200 165 190 160 180 150 170 145 165 135 150 ma ma 2.5 v curr (x18) curr (x32/x36) 175 200 165 190 160 180 150 170 145 165 135 150 ma ma
rev: 1.00b 12/2002 2/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 gs880f18b 100-pi n tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq b1 dq b2 v ss v ddq dq b3 dq b4 v dd nc v ss dq b5 dq b6 v ddq v ss dq b7 dq b8 dq b9 v ss v ddq v ddq v ss v ss dq a8 dq a7 v ss v ddq dq a6 dq a5 v ss nc v dd zz dq a4 dq a3 v ddq v ss dq a2 dq a1 v ss v ddq lbo a 5 a 4 a 3 a 2 a 1 a 0 nc nc v ss v dd nc a 17 a 10 a 11 a 12 a 13 a 14 a 16 a 6 a 7 e 1 e 2 nc nc b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a 8 a 9 a 15 512k x 18 top view dq a9 a 18 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc
rev: 1.00b 12/2002 3/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 gs880f32b 100-pin tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c4 dq c3 v ss v ddq dq c2 dq c1 v dd nc v ss dq d1 dq d2 v ddq v ss dq d3 dq d4 dq d5 v ss v ddq v ddq v ss dq b4 dq b3 v ss v ddq dq b2 dq b1 v ss nc v dd zz dq a1 dq a2 v ddq v ss dq a3 dq a4 v ss v ddq lbo a 5 a 4 a 3 a 2 a 1 a 0 nc nc v ss v dd nc a 17 a 10 a 11 a 12 a 13 a 14 a 16 a 6 a 7 e 1 e 2 b d b c b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a 8 a 9 a 15 256k x 32 top view dq b5 nc dq b7 dq b8 dq b6 dq a6 dq a5 dq a8 dq a7 nc dq c7 dq c8 dq c6 dq d6 dq d8 dq d7 nc dq c5 nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc
rev: 1.00b 12/2002 4/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 gs880f36b 100-pin tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c4 dq c3 v ss v ddq dq c2 dq c1 v dd nc v ss dq d1 dq d2 v ddq v ss dq d3 dq d4 dq d5 v ss v ddq v ddq v ss dq b4 dq b3 v ss v ddq dq b2 dq b1 v ss nc v dd zz dq a1 dq a2 v ddq v ss dq a3 dq a4 v ss v ddq lbo a 5 a 4 a 3 a 2 a 1 a 0 nc nc v ss v dd nc a 17 a 10 a 11 a 12 a 13 a 14 a 16 a 6 a 7 e 1 e 2 b d b c b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a 8 a 9 a 15 256k x 36 top view dq b5 dq b9 dq b7 dq b8 dq b6 dq a6 dq a5 dq a8 dq a7 dq a9 dq c7 dq c8 dq c6 dq d6 dq d8 dq d7 dq d9 dq c5 dq c9 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc
rev: 1.00b 12/2002 5/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 tqfp pin description symbol type description a 0 , a 1 i address field lsbs and address counter preset inputs a 2 ? a 17 i address inputs a 18 i address input dq a1 ? dq a9 dq b1 ? dq b9 dq c1 ? dq c9 dq d1 ? dq d9 i/o data input and output pins nc ? no connect bw ibyte write ? writes all enabled bytes; active low b a , b b, b c , b d i byte write enable for dq a , dq b data i/os; active low ck i clock input signal; active high gw i global write enable ? writes all bytes; active low e 1 i chip enable; active low g i output enable; active low adv i burst address counter advance enable; active low adsp , adsc i address strobe (processor, cache controller); active low zz i sleep mode control; active high lbo i linear burst order mode; active low v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply
rev: 1.00b 12/2002 6/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 gs880f18/32/36b block diagram a1 a0 a0 a1 d0 d1 q1 q0 counter load dq dq register register dq register dq register dq register dq register dq register dq register d q register d q register a0?an lbo adv ck adsc adsp gw bw e 1 g zz power down control memory array 36 36 4 a qd e 2 e 3 dqx1?dqx9 note: only x36 version shown for simplicity. 1 b a b b b c b d 0
rev: 1.00b 12/2002 7/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 note: there is a pull-down device on the zz pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables. burst counter sequences bpr 1999.05.18 byte wr ite truth table notes: 1. all byte outputs are active in read cycles regar dless of the state of byte write enable inputs. 2. byte write enable inputs b a , b b , b c , and/or b d may be used in any combination with bw to write single or multiple bytes. 3. all byte i/os remain high-z during all write operations regardless of the state of byte write enable inputs. 4. bytes ? c ? and ? d ? are only available on t he x32 and x36 versions. mode pin functions mode name pin name state function burst order control lbo l linear burst h interleaved burst power down control zz l or nc active h standby, i dd = i sb function gw bw b a b b b c b d notes read h h x x x x 1 read hlhhhh1 write byte a h l l h h h 2, 3 write byte b h l h l h h 2, 3 write byte c h l h h l h 2, 3, 4 write byte d h l h h h l 2, 3, 4 write all byteshlllll2, 3, 4 write all byteslxxxxx linear burst sequence note: the burst counter wraps to initial state on the 5th clock. i nterleaved burst sequence note: the burst counter wraps to initial state on the 5th clock. a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
rev: 1.00b 12/2002 8/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 synchronous truth table operation address used state diagram key 5 e 1 e 2 adsp adsc adv w 3 dq 4 deselect cycle, power down none x h x x l x x high-z deselect cycle, power down none x l f l x x x high-z deselect cycle, power down none x l f h l x x high-z read cycle, begin burst external r l t l x x x q read cycle, begin burst external r l t h l x f q write cycle, begin burst external w l t h l x t d read cycle, continue burst next cr x x h h l f q read cycle, continue burst next cr h x x h l f q write cycle, continue burst next cw x x h h l t d write cycle, continue burst next cw h x x h l t d read cycle, suspend burst current x x h h h f q read cycle, suspend burst current h x x h h f q write cycle, suspend burst current x x h h h t d write cycle, suspend burst current h x x h h t d notes: 1. x = don?t care, h = high, l = low 2. e = t (true) if e 2 = 1; e = f (false) if e 2 = 0 3. w = t (true) and f (false) is defined in the byte write truth table preceding 4. g is an asynchronous input. g can be driven high at any time to disable active output drivers. g low can only enable active drivers (shown as ?q? in the truth table above). 5. all input combinations shown above are tested and supported. in put combinations shown in gray boxes need not be used to accom plish basic synchronous or synchronous burst oper ations and may be avoided for simplicity. 6. tying adsp high and adsc low allows simple non-burst synchronous operations. see bold items above. 7. tying adsp high and adv low while using adsc to load new addresses allows simple burst operations. see italic items above.
rev: 1.00b 12/2002 9/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 first write first read burst write burst read deselect r w cr cw x x wr r wr x x x simple synchronous operation simple burst synchronous operation cr r cw cr cr simplified state diagram notes: 1. the diagram shows only supported (tested) synchr onous state transitions. the diagram presumes g is tied low. 2. the upper portion of the diagram assume s active use of only the enable (e1 , e2, and e3 ) and write (b a , b b , b c , b d , bw , and gw ) control inputs and that adsp is tied high and adsc is tied low. 3. the upper and lower portions of the diagram together a ssume active use of only the enable, write, and adsc control inputs and assumes adsp is tied high and adv is tied low.
rev: 1.00b 12/2002 10/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 first write first read burst write burst read deselect r w cr cw x x wr r w r x x x cr r cw cr cr w cw w cw simplified state diagram with g notes: 1. the diagram shows supported (tes ted) synchronous state transit ions plus supported transitions that depend upon the use of g . 2. use of ?dummy reads? (read cycles with g high) may be used to make the transition from read cycles to write cycles without passing through a deselect cycle. dummy read cycles increment the address counter just like normal read cycles. 3. transitions shown in grey tone assume g has been pulsed high long enough to turn the ram?s drivers off and for incoming data to meet data input set up time.
rev: 1.00b 12/2002 11/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ratings, for an exte nded period of tim e, may affect reliability of this component. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ? 0.5 to 4.6 v v ddq voltage in v ddq pins ? 0.5 to 4.6 v v i/o voltage on i/o pins ? 0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ? 0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/ ? 20 ma i out output current on any i/o pin +/ ? 20 ma p d package power dissipation 1.5 w t stg storage temperature ? 55 to 125 o c t bias temperature under bias ? 55 to 125 o c
rev: 1.00b 12/2002 12/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 power supply voltage ranges parameter symbol min. typ. max. unit notes 3.3 v supply voltage v dd3 3.0 3.3 3.6 v 2.5 v supply voltage v dd2 2.3 2.5 2.7 v 3.3 v v ddq i/o supply voltage v ddq3 3.0 3.3 3.6 v 2.5 v v ddq i/o supply voltage v ddq2 2.3 2.5 2.7 v notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. v ddq3 range logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 2.0 ? v dd + 0.3 v1 v dd input low voltage v il ? 0.3 ? 0.8 v 1 v ddq i/o input high voltage v ihq 2.0 ? v ddq + 0.3 v1,3 v ddq i/o input low voltage v ilq ? 0.3 ? 0.8 v 1,3 notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v. v ddq2 range logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 0.6*v dd ? v dd + 0.3 v1 v dd input low voltage v il ? 0.3 ? 0.3*v dd v1 v ddq i/o input high voltage v ihq 0.6*v dd ? v ddq + 0.3 v1,3 v ddq i/o input low voltage v ilq ? 0.3 ? 0.3*v dd v1,3 notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v.
rev: 1.00b 12/2002 13/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 note: these parameters are sample tested. notes: 1. junction temperature is a function of sr am power dissipation, package thermal resi stance, mounting board temperature, ambient . temper- ature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1 recommended operating temperatures parameter symbol min. typ. max. unit notes ambient temperature (com mercial range versions) t a 02570 c2 ambient temperature (industrial range versions) t a ? 40 25 85 c2 note: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. capacitance (t a = 25 o c, f = 1 mh z , v dd = 2.5 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 45pf input/output capacitance c i/o v out = 0 v 67pf package thermal characteristics rating layer board symbol max unit notes junction to ambient (at 200 lfm) single r ja 40 c/w 1,2 junction to ambient (at 200 lfm) four r ja 24 c/w 1,2 junction to case (top) ? r jc 9 c/w 3 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd + 2.0 v 50% v dd v il
rev: 1.00b 12/2002 14/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v ddq /2 output load fig. 1 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. device is deselected as defined by the truth table. dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ? 1 ua 1 ua zz input current i in1 v dd v in v ih 0 v v in v ih ? 1 ua ? 1 ua 1 ua 100 ua ft input current i in2 v dd v in v il 0 v v in v il ? 100 ua ? 1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ? 1 ua 1 ua output high voltage v oh2 i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh3 i oh = ? 8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v dq v ddq/2 50 ? 30pf * output load 1 * distributed test jig capacitance
rev: 1.00b 12/2002 15/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 operating currents notes: 1. i dd and i ddq apply to any combination of v dd3 , v dd2 , v ddq3 , and v ddq2 operation. 2. all parameters listed are worst case scenario. parameter test conditions mode symbol -5.5 -6 -6.5 -7 -7.5 -8.5 unit 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c operating current 3.3 v device selected; all other inputs v ih o r v il output open (x36/ x32) flow through i dd i ddq 180 20 190 20 170 20 180 20 165 15 175 15 155 15 165 15 150 15 160 15 140 10 150 10 ma (x18) flow through i dd i ddq 165 10 175 10 155 10 165 10 150 10 160 10 140 10 150 10 135 10 145 10 125 10 135 10 ma operating current 2.5 v device selected; all other inputs v ih o r v il output open (x36/ x32) flow through i dd i ddq 180 20 190 20 170 20 180 20 165 15 175 15 155 15 165 15 150 15 160 15 140 10 150 10 ma (x18) flow through i dd i ddq 165 10 175 10 155 10 165 10 150 10 160 10 140 10 150 10 135 10 145 10 125 10 135 10 ma standby current zz v dd ? 0.2 v flow through i sb 40 50 40 50 40 50 40 50 40 50 40 50 ma deselect current device deselected; all other inputs v ih or v il flow through i dd 60 65 50 55 50 55 50 55 50 55 45 50 ma
rev: 1.00b 12/2002 16/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 ac electrical characteristics notes: 1. these parameters are sampled and are not 100% tested. 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycl e, zz must meet the specified setup a nd hold times as specified above. parameter symbol -5.5 -6 -6.5 -7 -7.5 -8.5 unit min max min max min max min max min max min max flow through clock cycle time tkc 5.5 ? 6.0 ? 6.5 ? 7.0 ? 7.5 ? 8.5 ? ns clock to output valid tkq ? 5.5 ? 6.0 ? 6.5 ? 7.0 ? 7.5 ? 8.5 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns setup time ts 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns clock high time tkh 1.3 ? 1.3 ? 1.3 ? 1.3 ? 1.5 ? 1.7 ? ns clock low time tkl 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.7 ? 2 ? ns clock to output in high-z thz 1 1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns g to output valid toe ? 2.5 ? 2.7 ? 3.2 ? 3.5 ? 3.8 ? 4.0 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 2.5 ? 2.7 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? 20 ? 20 ? ns
rev: 1.00b 12/2002 17/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 flow through mode timing begin read a cont cont1 write b read c read c+1 read c+2 read c+3 read c cont2 deselect tkqx thz tkq tlz th ts tohz toe th ts th ts th ts th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh abc q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) q(c) e2 and e3 only sampled with adsc adsc initiated read deselected with e1 fixed high ck adsp adsc adv a0?an gw bw b a?b d e1 e2 e3 g dqa?dqd
rev: 1.00b 12/2002 18/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 sleep mode during normal operation, zz must be pulled low, either by the us er or by its internal pull down resistor. when zz is pulled hig h, the sram will enter a power sleep mode after 2 cycles. at this time, internal stat e of the sram is preserved. when zz returns t o low, the sram operates norma lly after zz recovery time. sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb 2. the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an async hronous, active high input that cau ses the device to enter sleep mo de. when the zz pin is driven high, i sb 2 is guaranteed after the time tzzi is met. because zz is an asynchronous input, pending operations or operations in progress may not be properly completed if zz is asserted. therefore, sleep mode must not be initiat ed until valid pending operations are completed. similarly, when exit ing sleep mode during tzzr, only a deselect or read commands may be applied while the sram is recovering from sleep mode. ck adsp adsc th tkh tkl tkc ts zz tzzr tzzh tzzs ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ snooze sleep mode timing diagram ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
rev: 1.00b 12/2002 19/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 tqfp package drawing d1 d e1 e pin 1 b e c l l1 a2 a1 y notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 ? 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch ? 0.65 ? l foot length 0.45 0.60 0.75 l1 lead length ? 1.00 ? y coplanarity ?? 0.10 lead angle 0 ? 7
rev: 1.00b 12/2002 20/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 ordering information for gs i synchronous burst rams org part number 1 type package speed 2 (mhz/ns) t a 3 status 512k x 18 gs880f18bt-5.5 flow through tqfp 5.5 c 512k x 18 gs880f18bt-6 flow through tqfp 6.0 c 512k x 18 gs880f18bt-6.5 flow through tqfp 6.5 c 512k x 18 gs880f18bt-7 flow through tqfp 7.0 c 512k x 18 gs880f18bt-7.5 flow through tqfp 7.5 c 512k x 18 gs880f18bt-8.5 flow through tqfp 8.5 c 256k x 32 gs880f32bt-5.5 flow through tqfp 5.5 c 256k x 32 gs880f32bt-6 flow through tqfp 6.0 c 256k x 32 gs880f32bt-6.5 flow through tqfp 6.5 c 256k x 32 gs880f32bt-7 flow through tqfp 7.0 c 256k x 32 gs880f32bt-7.5 flow through tqfp 7.5 c 256k x 32 gs880f32bt-8.5 flow through tqfp 8.5 c 256k x 36 gs880f36bt-5.5 flow through tqfp 5.5 c 256k x 36 gs880f36bt-6 flow through tqfp 6.0 c 256k x 36 gs880f36bt-6.5 flow through tqfp 6.5 c 256k x 36 gs880f36bt-7 flow through tqfp 7.0 c 256k x 36 gs880f36bt-7.5 flow through tqfp 7.5 c 256k x 36 gs880f36bt-8.5 flow through tqfp 8.5 c 512k x 18 gs880f18bt-5.5i flow through tqfp 5.5 i 512k x 18 gs880f18bt-6i flow through tqfp 6.0 i 512k x 18 gs880f18bt-6.5i flow through tqfp 6.5 i 512k x 18 gs880f18bt-7i flow through tqfp 7.0 i 512k x 18 gs880f18bt-7.5i flow through tqfp 7.5 i 512k x 18 gs880f18bt-8i flow through tqfp 8.5 i 256k x 32 gs880f32bt-5.5i flow through tqfp 5.5 i 256k x 32 GS880F32BT-6I flow through tqfp 6.0 i 256k x 32 gs880f32bt-6.5i flow through tqfp 6.5 i 256k x 32 gs880f32bt-7i flow through tqfp 7.0 i 256k x 32 gs880f32bt-7.5i flow through tqfp 7.5 i 256k x 32 gs880f32bt-8.5i flow through tqfp 8.5 i notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs880f18-6 t. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many differ ent configurations and with a vari ety of different features, on ly some of which are covered in this data sheet. see the gs i technology web site (www.gsitechnology.com ) for a complete listing of current offerings.
rev: 1.00b 12/2002 21/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 256k x 36 gs880f36bt-5.5i flow through tqfp 5.5 i 256k x 36 gs880f36bt-6i flow through tqfp 6.0 i 256k x 36 gs880f36bt-6.5i flow through tqfp 6.5 i 256k x 36 gs880f36bt-7i flow through tqfp 7.0 i 256k x 36 gs880f36bt-7.5i flow through tqfp 7.5 i 256k x 36 gs880f36bt-8.5i flow through tqfp 8.5 i org part number 1 type package speed 2 (mhz/ns) t a 3 status notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs880f18-6 t. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many differ ent configurations and with a vari ety of different features, on ly some of which are covered in this data sheet. see the gs i technology web site (www.gsitechnology.com ) for a complete listing of current offerings.
rev: 1.00b 12/2002 22/22 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs880f18/32/36bt-5 .5/6/6.5/7/7.5/8.5 9mb sync sram datasheet revision history ds/daterev. code: old; new types of changes format or content page;revisions;reason 880f18b_r1 ? creation of new datasheet

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